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TranslationMobile

掃描鏈

"scan" in Chinese : vt. (-nn-) 1.細(xì)看，細(xì)察；審視。 2.〔口語 ...
"chain" in Chinese : n. 1.鏈子，鏈條；項(xiàng)圈；表鏈。 2.連鎖；連續(xù)，一系 ...
"boundary-scan chain" in Chinese : 邊界掃描鏈
"slow scan camera chain" in Chinese : 慢掃描攝像機(jī)系統(tǒng)
"slow-scan camera chain" in Chinese : 慢掃描攝影電路
"a scan" in Chinese : 型掃描
"a-scan" in Chinese : a型掃掠; a型掃描; 形掃描
"are scan" in Chinese : 弧形掃描
"scan" in Chinese : vt. (-nn-) 1.細(xì)看，細(xì)察；審視。 2.〔口語〕大略一閱；瀏覽。 ...
"scan in" in Chinese : 掃描輸入
"scan-in" in Chinese : 掃描輸入; 掃入
"a chain" in Chinese : a鏈,重鏈:胰島素的兩個(gè)多肽鏈中的一個(gè)短鏈,含21個(gè)氨基酸,免疫球蛋白的重鏈 ...
"chain" in Chinese : n. 1.鏈子，鏈條；項(xiàng)圈；表鏈。 2.連鎖；連續(xù)，一系列，一連串；(山)脈 ...
"chain in" in Chinese : 鏈通道輸入
"the chain" in Chinese : 同命鎖鏈

Examples

Based on the addition algorithm , the design was optimized by the method of scan chain control and iterative invoke and realized 14 kinds of large - number operations such as addition , subtraction , multiplication , division , module addition , module multiplication , module exponential , etc
基于簡(jiǎn)單的加法操作，采用掃描鏈控制、迭代調(diào)用等方法對(duì)設(shè)計(jì)進(jìn)行優(yōu)化，實(shí)現(xiàn)了14種基本的大數(shù)運(yùn)算功能。
First , the low testing power dft solution - - scan array architecture are presented . in the scan array , the inserted wrapper and paralleled leaf scan chain reduce the testing power as low as the power dissipation in the normal working mode
首先，從優(yōu)化測(cè)試功耗的角度出發(fā)提出了掃描陣列結(jié)構(gòu)，通過加入wrapper測(cè)試控制結(jié)構(gòu)以及構(gòu)建并行化的分支掃描鏈，有效地將測(cè)試功耗降低到與正常工作功耗相當(dāng)?shù)牧考?jí)。
Chapter two detailedly presents the design of the boundary scan testing system which is in accordance with ieee . 1149 . correspondingly two special - used data registers are added , one of which is the scanning chain register and the other is the child scanning chain control - register
文中第二章按照ieee . 1149標(biāo)準(zhǔn)詳細(xì)設(shè)計(jì)了邊緣掃描測(cè)試系統(tǒng)，相應(yīng)增加了兩個(gè)專用數(shù)據(jù)寄存器，其中一個(gè)為掃描鏈寄存器，一個(gè)為掃描子鏈控制寄存器。
During test , some registers in the processor are converted into scan chains to improve controllability of the circuit , the adders in the processor are used as test generators , and the produced test patterns can detect any combinational faults within every basic building cell of fft processor
測(cè)試時(shí)，該方案將處理器中的寄存器作為掃描鏈提高了其可控性，利用其中的加法器作為測(cè)試生成，生成的測(cè)試矢量能偵測(cè)處理器每個(gè)基本組成單元內(nèi)部的任意組合失效。